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M67130/M67140
1 K 8 CMOS Dual Port RAM
Introduction
The M 67130/67140 are very low power CMOS dual port static RAMs organized as 1024 x 8. They are designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or more width systems. The TEMIC MASTER/SLAVE dual port approach in memory system applications results in full speed, error free operation without the need for additional discrete logic. Master and slave devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous access for reads and writes to any location in the memory. An automatic power down feature controlled by CS permits the onchip circuitry of each port in order to enter a very low stand by power mode. Using an array of eight transistors (8T) memory cell and fabricated with the state of the art 1.0 m lithography named SCMOS, the M67130/140 combine an extremely low standby supply current (typ = 1.0 A) with a fast access time at 35 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 5 W. For military/space applications that demand superior levels of performance and reliability the M 67130/140 is processed according to the methods of the latest revision of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D Fast access time 35 ns to 55 ns 30 ns preliminary for commercial only D 67130L/67140L low power 67130V/67140V very low power D Expandable data bus to 16 bits or more using master/slave devices when using more than one device. D On chip arbitration logic D BUSY output flag on master D D D D BUSY input flag on slave INT flag for port to port communication Fully asynchronous operation from either port Battery backup operation : 2 V data retention D TTL compatible D Single 5V 10 % Power Supply (1)
3.3 V versions are also available. Please consult sales.
MATRA MHS Rev. F (11 April. 97)
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M67130/M67140
Interface
Block Diagram
Notes : 1. M 67130 (MASTER) : BUSY is open drain output and requires pullup resistor M 67140 (SLAVE) : BUSY in input 2. Open drain output requires pull-up resistor
Pin Configuration
52 PIN PLCC (top view) 48 PIN LCC (top view)
48 PIN DIL (top view), ceramic, plastic 600 mils
CSL R/WL BUSYL INTL OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC CSR R/WR BUSYR INTR OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9L I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R
64 PIN VQFP (top view)
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MATRA MHS Rev. F (11 April. 97)
M67130/M67140
Pin Names
LEFT PORT
CSL R/WL OEL A0L - 9L I/O0L - 7L BUSYL INTL VCC GND
RIGHT PORT
CSR R/WR OER A0R - 9R I/O0R - 7R BUSYR INTR
NAMES
Chip select Write Enable Output Enable Address Data Input/Output Busy Flag Interrupt Flag Power Ground
Functional Description
The M 67130/M67140 has two ports with separate control, address and I/0 pins that permit independent read/write access to any memory location. These devices have an automatic power-down feature controlled by CS. CS controls on-chip power-down circuitry which causes the port concerned to go into stand-by mode when not selected (CS high). When a port is selected access to the full memory array is permitted. Each port has its own Output Enable control (OE). In read mode, the port's OE turns the Output drivers on when set LOW. Non-conflicting READ/WRITE conditions are illustrated in table 1.
The BUSY flags are required when both ports attempt to access the same location simultaneously.Should this conflict arise, on-chip arbitration logic will determine which port has access and set the BUSY flag for the inhibited port. BUSY is set at speeds that allow the processor to hold the operation with its associated address and data. It should be noted that the operation is invalid for the port for which BUSY is set LOW. The inhibited port will be given access when BUSY goes inactive. A conflict will occur when both left and right ports are active and the two addresses coincide. The on-chip arbitration determines access in these circumstances. Two modes of arbitration are provided : (1) if the addresses match and are valid before CS on-chip control logic arbitrates between CSL and CSR for access ; or (2) if the CSs are low before an address match, on-chip control logic arbitrates between the left and right addresses for access (refer to table 2). The inhibited port's BUSY flag is set and will reset when the port granted access completes its operation in both arbitration modes.
Data Bus Width Expansion Master/Slave Description
Expanding the data bus width to 16 or more bits in a dual-port RAM system means that several chips may be active simultaneously. If every chip has a hardware arbitrator, and the addresses for each chip arrive at the same time one chip may activate its L BUSY signal while another activates its R BUSY signal. Both sides are now busy and the CPUs will wait indefinitely for their port to become free. To overcome this "Busy Lock-Out" problem, MHS has developed a MASTER/SLAVE system which uses a single hardware arbitrator located on the MASTER. The SLAVE has BUSY inputs which allow direct interface to the MASTER with no external components, giving a speed advantage over other systems. When dual-port RAMs are expanded in width, the SLAVE RAMs must be prevented from writing until the BUSY input has been settled. Otherwise, the SLAVE chip may begin a write cycle during a conflict situation. On the opposite, the write pulse must extend a hold time beyond BUSY to ensure that a write cycle occurs once the conflict is resolved. This timing is inherent in all dual-port memory systems where more than one chip is active at the same time. The write pulse to the SLAVE must be inhibited by the MASTER's maximum arbitration time. If a conflict then occurs, the write to the SLAVE will be inhibited because of the MASTER's BUSY signal.
Interrupt Logic
The interrupt flag (INT) allows communication between ports or systems. If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is set when the right port writes to memory location 3FE (HEX). The left port clears the interrupt by reading address location 3FE. Similarly, the right port interrupt flag (INTR) is set when the left port writes to memory location 3FF (hex), and the right port must read memory location 3FF in order to clear the interrupt flag (INTR). The 8 bit message at 3FE or 3FF is user-defined. If the interrupt function is not used, address locations 3FE and 3FF are not reserved for mail boxes but become part of the RAM. See table 3 for the interrupt function.
Arbitration Logic
The arbitration logic will resolve an address match or a chip select match down to a minimum of 5 ns and determine which port has access. In all cases, an active BUSY flag will be set for the inhibited port.
MATRA MHS Rev. F (11 April. 97)
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M67130/M67140
Truth Table
Table 1 : Non Contention Read/Write Control(4)
LEFT OR RIGHT PORT(1) R/W
X L H H Notes :
CS
H L L L
OE
X X L H
D0-7
Z DATAIN DATAOUT Z
FUNCTION
Port Disabled and in Power Down Mode. ICCSB or ICCSB1 Data on Port Written into memory(2) Data in Memory Output on Port(3) High Impedance Outputs
1. AOL - A9L A0R - A9R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE.
Table 2 : Arbitration(6)
LEFT PORT CSL A0L - A9L
H L H L L L L L LL5R RL5L LW5R LW5R Notes : X Any X A0R - A9R LV5R RV5L Same Same = A0R - A9R = A0R - A9R = A0R - A9R = A0R - A9R
RIGHT PORT CSR A0L - A9R
H H L L L L L L LL5R RL5L LW5R LW5R X X Any A0L - A9L LV5R RV5L Same Same = A0L - A9L = A0L - A9L = A0L - A9L = A0L - A9L
FLAGS (5) BUSYL BUSYR
H H H H H L H L H L H L H H H H L H L H L H L H
FUNCTION
No Contention No Contention No Contention No Contention L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
5. INT Flags Don't Care. 6. X = DON'T CARE, L = LOW, H = HIGH. LV5R = Left Address Valid 5 ns before right address. RV5L = Right Address Valid 5 ns before left address. Same = Left and Right Addresses match within 5 ns of each other. LL5R = Left CS = LOW 5 ns before Right CS. RL5L = Right CS = LOW 5 ns before left CS. LW5R = Left and Right CS = LOWwithin 5 ns of each other.
Table 3 : Interrupt Flag (7, 10)
LEFT PORT R/WL
L X X X Notes : 7. 8. 9. 10.
RIGHT PORT INTL
X X L(9) H(8)
CSL
L X X L
OEL
X X X L
AOL-A9L
3FF X X 3FE
R/WR
X X L X
CSR
X L L X
OER
X L X X
AOR-A9R
X 3FF 3FE X
INTR
L(8) H(9) X X
FUNCTION
Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
Assumes BUSYL = BUSYR = H. If BUSYL = L, then NC. If BUSYR = L, then NC. H = HIGH, L = LOW, X = DON'T CARE, NC = NO CHANGE.
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MATRA MHS Rev. F (11 April. 97)
M67130/M67140
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC-GND) : . . . . . . . . . . . . . . . . . . -0.3 V to 7.0 V Input or output voltage applied : . . . (GND -0.3 V) to (VCC + 0.3 V) Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . -65C to + 150C * Notice Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extented periods may affect reliability.
OPERATING RANGE
Military Automotive Industrial Commercial
OPERATING SUPPLY VOLTAGE
VCC = 5 V 10 % VCC = 5 V 10 % VCC = 5 V 10 % VCC = 5 V 10 %
OPERATING TEMPERATURE
- 55 oC to + 125 oC - 40 oC to + 125 oC - 40 oC to + 85 oC 0 oC to + 70 oC
DC Parameters
67130/140-30 67130/140-35 67130/140-45 67130/140-55 Parameter Description Versio n Preliminary COM 5 40 100 1000 160 175 100 105 COM 5 40 100 1000 145 155 85 95 IND IND IND Unit Value MIL COM MIL COM MIL AUTO AUTO AUTO 5 50 200 2000 180 200 100 110 5 40 100 1000 135 150 75 85 5 50 200 2000 150 170 85 90 5 40 100 1000 130 140 70 80 5 50 200 2000 140 170 75 80 mA mA A A mA mA mA mA Max Max Max Max Max Max Max Max
ICCSB (11) ICCSB1 (12) ICCOP (13) ICCOP1 (14) Notes : 11. 12. 13. 14.
Standby supply current (Both ports TTL level inputs) Standby supply current (Both ports CMOS level inputs) Operating supply current (Both ports active) Operating supply current (One port active - One port standby)
V L V L V L V L
CSL = CSR 2.2 V. CSL = CSR VCC - 0.2 V. Both ports active - Maximum frequency - Outputs open - OE = VIH. One port active (f = fMAX) - Output open - One port stand-by TTL or CMOS Level inputs - CSL = CSR 2.2 V.
PARAMETER
II/O(15) VIL(16) VIH(16) VOL(17) VOL VOH(17) C IN(21) C OUT(21) Notes :
DESCRIPTION
Input/Output leakage current Input low voltage Input high voltage Output low voltage (I/O0-I/O7) Open drain output low voltage (BUSY, INT) IOL = 16 mA Output high voltage Input capacitance Output capacitance
67130-30/35/45/55 67140-30/35/45/55
+/- 10 0.8 2.2 0.4 0.5 2.4 5 7
UNIT
A V V V V V pF pF
VALUE
Max Max Min Max Max Min Max Max
15. VCC = 5.5 V, Vin = Gnd to VCC, CS = VIH, Vout = 0 to VCC. 16. VIH max = VCC + 0.3 V, VIL min - 0.3 V or -1 V pulse width 50 ns. 17. VCC min, IOL = 4 mA, IOH = -4 mA.
MATRA MHS Rev. F (11 April. 97)
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M67130/M67140
Data-Retention Mode
MHS CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention : 1 - Chip select (CS) must be held high during data retention ; within Vcc to VCCDR. 2 - CS must be kept between VCC - 0.2 V and 70 % of Vcc during the power up and power down transitions. 3 - The RAM can begin operation > tRC after Vcc reaches the minimum operating voltage (4.5 volts).
Timing
MAX PARAMETER TEST CONDITIONS (18) COM
ICCDR1 ICCDR2 @ VCCDR = 2 V @ VCCDR = 3 V 5 10
MIL IND AUTO
20 30
UNIT
A A
Notes : 18. CS = Vcc, Vin = Gnd to Vcc. 19. tRC = Read cycle time.
AC Test Conditions
Input Pulse Levels : GND to 3.0 V Input Rise/Fall Times : 5 ns Input Timing Reference Levels : 1.5 V Figure 1. Output Load. Output Reference Levels : 1.5 V Output Load : see figures 1, 2
Figure 2. Output load. (For tHZ, tLZ, tWZ, and tOW)
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MATRA MHS Rev. F (11 April. 97)
M67130/M67140
AC Parameters
READ CYCLE PARAMETER SYMBOL SYMBOL (23) (24) TAVAVR TAVQV TELQV TGLQV TAVQX TELQZ TEHQZ TPU TPD Notes : 20. 21. 22. 23. 24. (*). (**). tRC tAA tACS tAOE tOH tLZ tHZ tPU tPD Read cycle time Address access time Chip Select access time (22) Output enable access time Output hold from address change Output low Z time (20, 21) Output high Z time (20, 21) Chip Select to power up time (21) Chip disable to power down time (21) M67130-30(*) M67140-30(*) MIN. MAX. M67130-35(**) M67140-35(**) MIN. MAX. M67130-45 M67140-45 M67130-55 M67140-55
MIN. MAX. MIN. MAX. UNIT
PRELIMINARY 30 - - - 0 0 - 0 - - 30 30 15 - - 12 - 50 35 - - - 0 5 - 0 - - 35 35 25 - - 15 - 50 45 - - - 0 5 - 0 - - 45 45 30 - - 20 - 50 55 - - - 0 5 - 0 - - 55 55 35 - - 30 - 50 ns ns ns ns ns ns ns ns ns
Transition is measured 500 mV from low or high impedance voltage with load (figures 1 and 2). This parameter is guaranteed but not tested. To access RAM CS = VIL. STD symbol. ALT symbol. Commercial only, not available in DIP. DIP package available for commercial only.
Timing Waveform of Read Cycle no 1, Either Side (25, 26, 28)
Timing Waveform of Read Cycle no 2, Either Side (25, 27, 29)
Notes :
25. 26. 27. 28. 29.
R/W is high for read cycles. Device is continuously enabled, CS = VIL. Addresses valid prior to or coincident with CS transition low. OE = VIL. To access RAM, CS = VIL.
MATRA MHS Rev. F (11 April. 97)
7
M67130/M67140
AC Parameters
WRITE CYCLE PARAMETER SYMBOL SYMBOL (34) (35) TAVAVW TELWH TAVWH TAVWL TWLWH TWHAX TDVWH TGHQZ TWHDX TWLQZ TWHQX Notes : tWC tSW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write cycle time Chip select to end of write (32) Address valid to end of write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to end of write Output high Z time (30, 31) Data hold time (33) Write enable to output in high Z (30, 31) Output active from end of write (30, 31, 33) M67130-30(*) M67140-30(*) MIN. MAX. M67130-35(**) M67140-35(**) MIN. MAX. M67130-45 M67140-45 M67130-55 M67140-55
MIN. MAX. MIN. MAX. UNIT
PRELIMINARY 30 25 25 0 25 0 15 - 0 - 0 - - - - - - - 12 - 12 - 35 30 30 0 30 0 20 - 0 - 0 - - - 15 - 15 - - 45 35 35 0 35 0 20 - 0 - 0 - - - - - - - 20 - 20 - 55 40 40 0 40 0 20 - 0 - 0 - - - - - - 30 - 30 - ns ns ns ns ns ns ns ns ns ns ns
30. Transition is measured 500 mV from low or high impedance voltage with load (figures 1 and 2). 31. This parameter is guaranteed but not tested. 32. To access RAM CS = VIL. This condition must be valid for entire tSW time. 33. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 34. STD symbol. 35. ALT symbol. (*). Commercial only. Not available in DIP. (**). DIP package available for commercial only.
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MATRA MHS Rev. F (11 April. 97)
M67130/M67140
Timing Waveform of Write Cycle no 1, R/W Controlled Timing (36, 37, 38, 42)
tWC ADDRESS tHZ(41) OE tAW CS (43) tAS R/W tWP(42) tWR
tWZ(41) tOW DATAOUT (39) tDW DATAIN tDH (39)
Timing Waveform of Write Cycle no 2, CS Controlled Timing (36, 37, 38, 40)
tWC ADDRESS tAW CS (43)
tAS R/W
tSW
tWR
tDW DATAIN
tDH
Notes :
R/W must be high during all address transitions. A write occurs during the overlap (tSW or tWP) of a low CS and a low R/W. tWR is measured from the earlier of CS or R/W going high to the end of write cycle. During this period, the I/O pins are in the output state, and input signals must not be applied. If the CS low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. 41. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 % tested. 42. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 43. To access RAM, CS = VIL.
36. 37. 38. 39. 40.
MATRA MHS Rev. F (11 April. 97)
9
M67130/M67140
AC Parameters
Symbol PARAMETER M67130-30(*) M67140-30(*) MIN. BUSY TIMING (F M67130 only) (For l) PRELIMINARY tBAA tBDA tBAC tBDC tWDD tDDD tAPS tBDD BUSY Access time to address BUSY Disable time to address BUSY Access time to Chip Select BUSY Disable time to Chip Select Write Pulse to data delay (44) Write data valid to read data delay (44) Arbitration priority set-up time (45) BUSY disable to valid data BUSY TIMING (For M 67140 only) tWB tWH tWDD tDDD Notes : Write to BUSY input (47) Write hold after BUSY (48) Write pulse to data delay (49) Write data valid to read data delay (49) 0 20 - - - - 55 30 0 20 - - - - 60 35 0 20 - - - - 70 45 0 20 - - - - 80 55 - - - - - - 5 - 30 25 25 25 55 33 - Note 46 - - - - - - 5 - 35 30 30 25 60 35 - Note 46 - - - - - - 5 - 35 35 30 25 70 45 - Note 46 - - - - - - 5 - 45 40 35 30 80 55 - Note 46 ns ns ns ns ns ns ns ns ns ns ns ns ns MAX. M67130-35 M67140-35 MIN. MAX. M67130-45 M67140-45 MIN. MAX. M67130-55 M 67140-55 MIN. MAX. UNIT
44. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read with BUSY (For M67130 only)". 45. To ensure that the earlier of the two ports wins. 46. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). 47. To ensure that the write cycle is inhibited during contention. 48. To ensure that a write cycle is completed after contention. 49. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveforms of Read with Port to port delay (For M67140 only)". (*). Commercial only. Not available in DIP. (**). DIP package available for commercial only.
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MATRA MHS Rev. F (11 April. 97)
M67130/M67140
Timing Waveform of Read with BUSY (50, 51, 52) (For M67130)
TWC ADDRR MATCH
R/WR
tWP
tDW DATAIN R tAPS ADDRL (50) MATCH tBDA VALID
tDH
tBDD
BUSYL tWDD DATAOUT L tDDD(53) VALID
Notes :
50. 51. 52. 53.
To ensure that the earlier of the two port wins. Write cycle parameters should be adhered to, to ensure proper writing. Device is continuously enabled for both ports. OE at L for the reading port.
Timing Waveform of Write with Port-to-port (54, 55, 56) (For M67140 only)
TWC ADDRR MATCH
R/WR
tWP
tDW DATAIN R VALID
tDH
ADDRL
MATCH
tWDD DATAOUT L tDDD VALID
Notes :
54. Assume BUSY = H for the writing port, and OE = L for the reading port. 55. Write cycle parameters should be adhered to, to ensure proper writing. 56. Device is continuously enabled for both ports.
MATRA MHS Rev. F (11 April. 97)
11
M67130/M67140
Timing Waveform of Write with BUSY (For M67140)
Timing Waveform of Contention Cycle no 1, CS Arbitration (For M67130 only)
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MATRA MHS Rev. F (11 April. 97)
M67130/M67140
Timing Waveform of Contention Cycle no 2, Address Valid Abritration (For M67130 only) (57) Left Address Valid First :
Right Address Valid First :
Note :
57. CSL = CSR = VIL
16 Bit Master/Slave Dual-port Memory Systems
Note :
58. No arbitration in M67140 (SLAVE). BUSY-IN inhibits write in M67140 (SLAVE).
MATRA MHS Rev. F (11 April. 97)
13
M67130/M67140
Waveform of Interrupt Timing (59)
Notes :
59. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from "A". 60. See interrupt thruth table. 61. Timing depends on which enable signal is asserted last. 62. Timing depends on which enable signal is de-asserted first.
AC Electrical Characteristics over the Full Operating Temperature and Supply Voltage Range
INTERRUPT TIMING SYMBOL
tAS tWR tINS tINR Address set-up time Write recovery time Interrupt set time Interrupt reset time
PARAMETER
67130/140-30 (*) MIN.
0 0 - -
67130/140-35 (**) MIN.
0 0 - -
67130/140-45 MIN.
0 0 - -
67130/140-55 UNIT MIN.
0 0 - -
MAX.
- - 30 30
MAX.
- - 35 35
MAX.
- - 40 40
MAX.
- - 45 45 ns ns ns ns
(*). Commercial only. Not available in DIP. (**). DIP package available for commercial only.
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MATRA MHS Rev. F (11 April. 97)
M67130/M67140
Ordering Information
TEMPERATURE RANGE C M PACKAGE S3 DEVICE 67130V SPEED 35 FLOW
1K = 48 pin DIL ceramic 600 mils 30 ns CK = 48 pin DIL side-brazed 600 mils 35 ns 4K = 48 pin LCC 45 ns S3 = 52 pin PLCC 55 ns 3K = 48 pin DIL plastic 600 mils RD = 64 pin VQFP KK = Flat pack 48 pins 400 mils67130 = 8K (1K x 8) Master Q3 = CQPJ 52 67140 = 8K (1K x 8) Slave 0 = Dice form L = Low power V = Very low power blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX :R : RD :D = = = = = = = = = = = = MHS standards MIL STD 883 Class B or S MIL STD 883 + PIND test SCC 9000 level B/C Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape and reel Tape and reel dry pack Dry pack
C = Commercial I = Industrial A = Automotive M = Military S = Space
0 -40 -40 -55 -55
to to to to to
+70C +85C +125C +125C +125C
MATRA MHS Rev. F (11 April. 97)
15
M67130/M67140
Military and Space Versions
The following tables give package/consumption/access time/process flow available combinations
Temp. range Packages Consumption
V L
Access Time (ns)
35 45 55
Std process 67130
Mil flows (including SMD5962-86875) D D D X D D D D X D
RT process 67130E
Mil flows Space flows
M
1K 4K CK KK Q3 0 4K CK KK 0
D D D X D X D D X X
D D D X D D
D D D X D X
D D D X D X D D X X
D D D X D D D D X D
S
D
D D X D
Temp. range
Packages
Consumption
V L
Access Time (ns)
35 45 55
Std process 67140
Mil flows (including SMD5962-86875) D D D X D D D D X D
RT process 67140E
Mil flows Space flows
M
1K 4K CK KK Q3 0 4K CK KK 0
D D D X D X D D X X
D D D X D D
D D D X D X
D D D X D X D D X X
D D D X D D D D X D
S
D
D D X D
D = product in production X = call sales office for availibility
The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
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MATRA MHS Rev. F (11 April. 97)

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